P (power loss) = I² (electric current) R (internal resistance)

The larger the size of wafer and cell, the higher the electric current will be - and therefore the higher the heat loss inside the module. Controlling the heat loss can bring about a significant power gain and, given this need, "half-cut” technology emerged, to halve the electric current of about 9.4A to 4.7A (i.e., the entire cell of 156.75 mm (M2) is changed to half cell), thereby increasing the power of the module by about 2% and controlling to a certain extent the cost for solder strips and bus bars. Such "half-cut” technology is subject to symmetrical cutting, that is, the half cells formed have a good consistency and a smaller loss, which can represent the optimal cutting technology (so-called non-destructive cutting technology can never completely eliminate loss).

Based on the drop in electric current and the control of loss achieved by the half-cut technology, the development history of moderately increasing the dimension of the module - 166mm wafer size cell (area/current increased by about 12%) and 182mm wafer size cell (area/current increased by about 35%) - has evolved, with a certain increase in current and heat loss inside. However, the area that is ineffective in generating power is narrowed down by the increase in the areas of cell and module, which brings about an increase in efficiency of the module as a whole. When packaged with smart soldering technology, the 182mm wafer size module has reached an average efficiency of 21% in mass production.

Excessive increase of the area of a cell (for example, an increase of more than 80% with 210mm cell comparing to standard M2), will cause a significant increase in power loss caused by internal heating inside the module, which will in turn lower the efficiency (in mass production) by 0.2~0.4%, compared with a 182mm wafer size module, leading to a rise in operating temperature. This practice is therefore not considered a wise choice.  

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